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DEVICE SPECIFICATION
QUAD GIGABIT ETHERNET DEVICE QUAD GIGABIT ETHERNET DEVICE GENERAL DESCRIPTION
S2204 S2204
FEATURES
* 1250 MHz (Gigabit Ethernet) operating rate www..com Operation - 1/2 Rate * Quad Transmitter with phase-locked loop (PLL) clock synthesis from low speed reference * Quad Receiver PLL provides clock and data recovery * Internally series terminated TTL outputs * Low-jitter serial PECL interface * Individual local loopback control * JTAG 1149.1 Boundary scan on low speed I/O signals * Interfaces with coax, twinax, or fiber optics * Single +3.3V supply, 2.5 W power dissipation * Compact 23mm x 23mm 208 TBGA package
The S2204 facilitates high-speed serial transmission of data in a variety of applications including Gigabit Ethernet, serial backplanes, and proprietary point to point links. The chip provides four separate transceivers which can be operated individually for a data capacity of >4 Gbps. Each bi-directional channel provides parallel to serial and serial to parallel conversion, clock generation/ recovery, and framing. The on-chip transmit PLL synthesizes the high-speed clock from a low-speed reference. The on-chip quad receive PLL is used for clock recovery and data re-timing on the four independent data inputs. The transmitter and receiver each support differential PECL-compatible I/O for copper or fiber optic component interfaces with excellent signal integrity. Local loopback mode allows for system diagnostics. The chip requires a 3.3V power supply and dissipates 2.5 watts. Figure 1 shows the S2204 and S2004 in a Gigabit Ethernet application. Figure 2 combines the S2204 with a crosspoint switch to demonstrate a serial backplane application. Figure 3 is the input/ output diagram. Figures 4 and 5 show the transmit and receive block diagrams, respectively.
APPLICATIONS
* * * * * * Ethernet Backbones Workstation Frame buffer Switched networks Data broadcast environments Proprietary extended backplanes
Figure 1. Typical Quad Gigabit Ethernet Application
GE INTERFACE SERIAL BP DRIVER
MAC
(ASIC)
QUAD GIGABIT ETHERNET INTERFACE
MAC
(ASIC)
TO SERIAL BACKPLANE
S2204 MAC
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S2004
MAC
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S2204
Figure 2. Typical Backplane Application
MAC
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QUAD GIGABIT ETHERNET DEVICE
MAC
(ASIC)
MAC ATM Ethernet Etc.
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MAC
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S2204 MAC
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S2004
S2004 MAC
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S2204
ATM Ethernet Etc.
MAC
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MAC
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Crosspoint Switch S2016 S2025 MAC
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MAC
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ATM Ethernet Etc.
MAC
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MAC
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S2204 MAC
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S2004
S2004 MAC
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S2204
ATM Ethernet Etc.
MAC
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BACKPLANE SIGNAL GROUP
MAC
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Figure 3. S2204 Input/Output Diagram
TRS TMS TCK TDI TDO
S2204
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RESET RATE
REFCLK CLKSEL TMODE
TXAP/N
TCLKO TXBP/N DINA[0:9] TBCA TXCP/N DINB[0:9] TBCB
10 10
DINC[0:9] TBCC
10
TXDP/N
DIND[0:9] TBCD COM_DETA DOUTA[0:9] RBC1/0A
10
RXAP/N
10
RXBP/N COM_DETB DOUTB[0:9] RBC1/0B RXCP/N COM_DETC DOUTC[0:9] RBC1/0C COM_DETD DOUTD[0:9] RBC1/0D
10 10 10
RXDP/N
TESTMODE TESTMODE1 CMODE
LPENA LPENB LPENC LPEND
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Figure 4. Transmitter Block Diagram
RATE REFCLK www..com CLKSEL
DIN PLL 10x/20x
QUAD GIGABIT ETHERNET DEVICE
REFCLK
TCLKO TMODE TMODE 10 DINA[0:9] FIFO
(input)
10
Shift Reg
TXAP TXAN TXABP
01
TBCA 10 DINB[0:9] FIFO
(input)
10
Shift Reg
TXBP TXBN TXBBP
01
TBCB 10 DINC[0:9] FIFO
(input)
10
Shift Reg
TXCP TXCN TXCBP
01
TBCC 10 DIND[0:9] FIFO
(input)
10 TXDP
Shift Reg
TXDN TXDBP
01
TBCD
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Figure 5. Receiver Block Diagram
TMODE
S2204
CMODE
www..com RATE
REFCLK RBC1/0A COM_DETA
2 TXABP FIFO
(output) 10
10 DOUTA[0:9] Q
DOUT CRU SerialParallel
RXAP RXAN LPENA
2 RBC1/0B COM_DETB FIFO
(output) 10
TXBBP
DOUT CRU SerialParallel
10 DOUTB[0:9]
RXBP RXBN
RBC1/0C COM_DETC
2
LPENB
FIFO
(output)
TXCBP
10
10 DOUTC[0:9]
DOUT CRU SerialParallel
RXCP RXCN
LPENC RBC1/0D COM_DETD FIFO
(output) 10
2 TXDBP
DOUT CRU SerialParallel
10 DOUTD[0:9]
RXDP RXDN
LPEND
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S2204 TRANSMITTER DESCRIPTION
The transmitter section of the S2204 contains a single PLL which is used to generate the serial rate transmit clock for all transmitters. Four channels are www..com provided with a variety of options regarding input clocking and loopback. The transmitters operate at 1.250 GHz, 10 or 20 times the reference clock frequency.
QUAD GIGABIT ETHERNET DEVICE
Figure 6 demonstrates the flexibility afforded by the S2204. A low jitter reference is provided directly to the S2204 at either 1/10 or 1/20 the serial data rate. This insures minimum jitter in the synthesized clock used for serial data transmission. A system clock output at the parallel word rate, TCLKO, is derived from the PLL and provided to the upstream circuit as a system clock. The frequency of this output is constant at the parallel word rate, 1/10 the serial data rate, regardless of whether the reference is provided at 1/10 or 1/20 the serial data rate. This clock can be buffered as required without concern about added delay. There is no phase requirement between TCLKO and TBCx, which is provided back to the S2204, other than that they remain within 3 ns of the phase relationship established at reset. The S2204 also supports the traditional REFCLK clocking found in many Gigabit Ethernet applications and is illustrated in Figure 7.
Data Input
The S2204 has been designed to simplify the parallel interface data transfer and provides the utmost in flexibility regarding clocking of parallel data. The S2204 incorporates a unique FIFO structure on both the parallel inputs and the parallel outputs which enables the user to provide a "clean" reference source for the PLL and to accept a separate external clock which is used exclusively to reliably clock data into the device. Data is input to each channel of the S2204 nominally as a 10 bit wide word. An input FIFO and a clock input, TBCx, are provided for each channel of the S2204. The device can operate in two different modes. The S2204 can be configured to use either the TBCx (TBC MODE) input or the REFCLK input (REFCLK MODE). Table 1 provides a summary of the input modes for the S2204. Operation in the TBC MODE makes it easier for users to meet the relatively narrow setup and hold time window required by the 125 Mbps 10-bit interface. The TBC signal is used to clock the data into an internal holding register and the S2204 synchronizes its internal data flow to insure stable operation. However, regardless of the clock mode, REFCLK is always the VCO reference clock. This facilitates the provision of a clean reference clock resulting in minimum jitter on the serial output. The TBC must be frequency locked to REFCLK, but may have an arbitrary phase relationship. Adjustment of internal timing of the S2204 is performed during reset. Once synchronized, the user must insure that the timing of the TBC signal does not change by more than 3 ns relative to the REFCLK.
Half Rate Operation
The S2204 supports full and 1/2 rate operation for all modes of operation. When RATE is LOW, the S2204 serial data rate equals the VCO frequency. When RATE is HIGH, the VCO is divided by 2 before being provided to the chip. Thus the S2204 can support Gigabit Ethernet and serial backplane functions at both full and 1/2 the VCO rate. See Table 3.
Parallel to Serial Conversion
The 10-bit parallel data handled by the S2204 device should be from a DC-balanced encoding scheme, such as the 8B/10B transmission code, in which information to be transmitted is encoded, 8 bits at a time, into a 10bit transmission character and must be compliant with IEEE 802.3z Gigabit Ethernet. The 8B/10B transmission code includes serial encoding and decoding rules, special characters, and error control. Information is encoded, 8 bits at a time, into a 10 bit transmission character. The characters defined by this code ensure that short run lengths and enough transitions are present in the serial bit stream to make clock recovery possible at the receiver. The encoding also greatly increases the likelihood of detecting any single or multiple errors that might occur during the transmission and reception of data1.
1. A.X. Widner and P.A. Franaszek, "A Byte-Oriented DC Balanced (0,4) 8B/10B Transmission Code," IBM Research Report RC9391, May 1982.
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Table 2 identifies the mapping of the 8B/10B characters to the data inputs of the S2204. The S2204 will serialize the parallel data for each channel and will transmit bit "a" or DIN[0] first.
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S2204
Table 1. Input Modes
TMODE Operation REFCLK MODE. REFCLK used to clock data into FIFOs for all channels. TBC MODE. TBCx used to clock data into FIFOs for all channels.
Frequency Synthesizer (PLL)
The S2204 synthesizes a serial transmit clock from the reference signal. Upon startup, the S2204 will obtain phase and frequency lock within 2500 bit times after the start of receiving reference clock inputs. Reliable locking of the transmit PLL is assured, but a lock-detect output in NOT provided.
0
1
1. Note that internal synchronization of FIFOs is performed upon de-assertion of RESET.
Figure 6. DIN Data Clocking with TBC
125 MHz or 62.5 MHz REF OSCILLATOR
Figure 7. DIN Clocking with REFCLK
125 MHz REF OSCILLATOR
REFCLK TCLKO
PLL
REFCLK TCLKO
PLL
DINx[0:9]
DINx[0:9]
TBCx
TBCx
MAC ASIC
S2204
MAC ASIC
S2204
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QUAD GIGABIT ETHERNET DEVICE
Table 2. Data to 8B/10B Alphabetic Representation
Data Byte DIN[0:9] or DOUT[0:9] 0 a 1 b 2 c 3 d 4 e 5 i 6 f 7 g 8 h 9 j
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8B/10B Alphanumeric Representation
Reference Clock Input
The reference clock input must be supplied with a low-jitter clock source. All reference clocks in a system must be within 200 ppm of each other to insure that the clock recovery units can lock to the serial data. The frequency of the reference clock must be either 1/10 the serial data rate, CLKSEL = 0, or 1/20 the serial data rate, CLKSEL=1. In both cases the frequency of the parallel word rate output, TCLKO, is constant at 1/10 the serial data rate. See Table 3.
Serial Data Outputs
The S2204 provides LVPECL level serial outputs. The serial outputs do not require output pulldown resistors. Outputs are designed to perform optimally when AC-coupled.
Transmit FIFO Initialization
The transmit FIFO must be initialized after stable delivery of data and TBC to the parallel interface, and before entering the normal operational state of the circuit. FIFO initialization is performed upon the de-assertion of the RESET signal. TCLKO will operate normally regardless of the state of RESET.
Table 3. Operating Rates
RATE 0 0 1 1 CLKSEL 0 1 0 1 REFCLK Serial TCLKO Frequency Output Rate Frequency 125 MHz 62.5 MHz 62.5 MHz 31.25 MHz 1250 MHz 1250 MHz 625 MHz 625 MHz 125 MHz 125 MHz 62.5 MHz 62.5 MHz
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QUAD GIGABIT ETHERNET DEVICE RECEIVER DESCRIPTION
Each receiver channel is designed to implement a Serial Backplane receiver function through the physical layer. A block diagram showing the basic funcwww..com tion is provided in Figure 5. Whenever a signal is present, the receiver attempts to recover the serial clock from the received data stream. After acquiring bit synchronization, the S2204 searches the serial bit stream for the occurrence of a K28.5 character on which to perform word synchronization. Once synchronization on both bit and word boundaries is achieved, the receiver provides the word-aligned data on its parallel outputs.
S2204
The "lock to reference" frequency criteria ensure that the S2204 will respond to variations in the serial data input frequency (compared to the reference frequency). The new Lock State is dependent upon the current lock state, as shown in Table 4. The run-length criteria insure that the S2204 will respond appropriately and quickly to a loss of signal. The run-length checker flags a condition of consecutive ones or zeros across 12 parallel words. Thus 119 or less consecutive ones or zeros does not cause signal loss, 129 or more causes signal loss, and 120 - 128 may or may not, depending on how the data aligns across byte boundaries. If both the off-frequency detect circuitry test and the run-length test are satisfied, the CRU will attempt to lock to the incoming data. It is possible for the run length test to be satisfied due to noise on the inputs, even if no signal is present. In this case the receiver VCO will maintain frequency accuracy to within 100 ppm of the target rate as determined by REFCLK. In any transfer of PLL control from the serial data to the reference clock, the RBC1/0x outputs remain phase continuous and glitch free, assuring the integrity of downstream clocking.
Data Input
A differential input receiver is provided for each channel of the S2204. Each channel has a loopback mode in which the serial data from the transmitter replaces external serial data. The loopback function for each channel is enabled by its respective LPEN input. The high speed serial inputs to the S2204 are internally biased to VDD-1.3V. All that is required externally are AC-coupling and line-to-line differential termination.
Clock Recovery Function
Clock recovery is performed on the input data stream for each channel of the S2204. The receiver PLL has been optimized for the anticipated needs of Serial Backplane systems. A simple state machine in the clock recovery macro decides whether to acquire lock from the serial data input or from the reference clock. The decision is based upon the frequency and run length of the serial data inputs. If at any time the frequency or run length checks are violated, the state machine forces the VCO to lock to the reference clock. This allows the VCO to maintain the correct frequency in the absence of data.
Reference Clock Input
A single reference clock, which serves both transmitter and receiver, must be provided from a low jitter clock source. The frequency of the received data stream (divided-by -10 or -20) must be within 200 ppm of the reference clock to insure reliable locking of the receiver PLL.
Serial to Parallel Conversion
Once bit synchronization has been attained by the S2204 CRU, the S2204 must synchronize to the 10 bit word boundary. Word synchronization in the S2204 is accomplished by detecting and aligning to the 8B/10B K28.5 codeword. The S2204 will detect and byte-align to either polarity of the K28.5. Each channel of the S2204 will detect and align to a K28.5 anywhere in the data stream. The presence of a K28.5 is indicated for each channel by the assertion of the COM_DETx signal.
Table 4. Lock to Reference Frequency Criteria
Current Lock State PLL Frequency (vs. REFCLK) < 488 ppm Locked 488 to 732 ppm > 732 ppm < 244 ppm Unlocked 244 to 366 ppm > 366 ppm New Lock State Locked Undetermined Unlocked Locked Undetermined Unlocked
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S2204
Data Output
Data is output on the DOUT[0:9] outputs. The COM_DET signal is used to indicate the reception of a valid K28.5 character. The S2204 TTL outputs are optimized to drive 65 line impedances. Internal source matching provides good performance on unterminated lines of reasonable length.
QUAD GIGABIT ETHERNET DEVICE OTHER OPERATING MODES
Operating Frequency Rate
The S2204 is designed to operate at the Gigabit Ethernet rate of 1.250 GHz.
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Loopback Mode
When loopback mode is enabled, the serial data from the transmitter is provided to the serial input of the receiver, as shown in Figure 8. This provides the ability to perform system diagnostics and off-line testing of the interface to verify the integrity of the serial channel. Loopback mode is enabled independently for each channel using its respective loopback-enable input, LPEN.
Parallel Output Clock Rate
Two output clock modes are supported, as shown in Table 5. When CMODE is High, a complementary TTL clock at the data rate is provided on the RBC1/0x outputs. Data should be clocked on the rising edge of RBC1x. When CMODE is Low, a complementary TTL clock at 1/2 the data rate is provided. Data should be latched on the rising edge of RBC1x and the rising edge of RBC0x. In Gigabit Ethernet applications, multiple consecutive K28.5 characters cannot be generated. However, for serial backplane applications this can occur. The S2204 must be able to operate properly when multiple K28.5 characters are received. After the first K28.5 is detected and aligned, the RBC1/0x clock will operate without glitches or loss of cycles.
TEST MODES
The RESET pin is used to initialize the Transmit FIFOs and must be asserted (LOW) prior to entering the normal operational state (see section Transmit FIFO Initialization).
Figure 8. S2204 Diagnostic Loopback Operation
CSU
External Receiver Clocking
An external clock can be provided to the S2204 to clock the parallel receive data, DOUT[0:9], out of the device. External Clock mode is enabled when TMODE = Low. Table 5A describes the receiver output clocking options available. When TBCA is used as the output clock source, the REFCLK and TBCA frequency must equal the parallel word rate, CLKSEL = Low. The RBC1/0x outputs will provide a buffered copy of the output clock.
CRU
Note: Serial output data remains active during loopback operation to enable other system tests to be performed.
Table 5. Output Clock Mode (TMODE = 1)
Mode Half Clock Mode Full Clock Mode
CMODE 0 1
RBC1/0x Freq 62.5 MHz 125 MHz
Table 5A. S2204 Data Clocking
TMODE 0 1 Input Clock Source REFCLK TBCx Output Clock Source TBCA RBCx
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QUAD GIGABIT ETHERNET DEVICE JTAG TESTING
The JTAG implementation for the S2204 is compliant with the IEEE1149.1 requirements. JTAG is used to test the connectivity of the pins on the chip. The www..com TAP, (Test Access Port), provides access to the test logic of the chip. When TRST is asserted the TAP is initialized. TAP is a state machine that is controlled by TMS. The test instruction and data are loaded through TDI on the rising edge of TCK. When TMS is high the test instruction is loaded into the instruction register. When TMS is low the test data is loaded into the data register. TDO changes on the falling edge of TCK. All input pins, including clocks, that have boundary scan are observe only. They can be sampled in either normal operational or test mode. All output pins that have boundary scan, are observe and control. They can be sampled as they are driven out of the chip in normal operational mode, and they can be driven out of the chip in test mode using the Extest instruction. Since JTAG testing operates only on digital signals there are some pins with analog signals that JTAG does not cover. The JTAG implementation has the three required instruction, Bypass, Extest, and Sample/Preload. Instruction BYPASS EXTEST SAMPLE/PRELOAD ID CODE Code 11 00 01 10
S2204
JTAG Instruction Description:
The BYPASS register contains a single shift-register stage and is used to provide a minimum-length serial path between the TDI and TDO pins of a component when no test operation of that component is required. This allows more rapid movement of test data to and from other components on a board that are required to perform test operations. The EXTEST instruction allows testing of off-chip circuitry and board level interconnections. Data would typically be loaded onto the latched parallel outputs of boundary-scan shift-register stages using the SAMPLE/PRELOAD instruction prior to selection of the EXTEST instruction. The SAMPLE/PRELOAD instruction allows a snapshot of the normal operation of the component to be taken and examined. It also allows data values to be loaded onto the latched parallel outputs of the boundary-scan shift register prior to selection of the other boundary-scan test instructions. The following table provides a list of the pins that are JTAG tested. Each port has a boundary scan register (BSR), unless otherwise noted. The following features are described: the JTAG mode of each register (input, output2, or internal (refers to an internal package pin)), the direction of the port if it has a boundary scan register (in or out), and the position of this register on the scan chain.
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S2204
Table 6. JTAG Pin Assignments
S2204 Pin Name TESTMODE1 CMODE www..com TESTMODE LPEND LPENC LPENB LPENA CLKSEL TMODE Core_Scan Port Name sync cmode chan_lock lpend lpenc lpenb lpena clksel tmode JTAG Mode Input Input Input Input Input Input Input Input Input Internal RESET REFCLK TCLKO DIND9 DIND8 DIND7 DIND6 DIND5 DIND4 DIND3 DIND2 DIND1 DIND0 TBCD DINC9 DINC8 DINC7 DINC6 DINC5 DINC4 DINC3 DINC2 DINC1 DINC0 TBCC DINB8 DINB9 DINB7 DINB6 DINB5 reset refclk transmit_clk_ buf_out dnd kgend tdatain_d (7) tdatain_d (6) tdatain_d (5) tdatain_d (4) tdatain_d (3) tdatain_d (2) tdatain_d (1) tdatain_d (0) tclkd dnc kgenc tdatain_c (7) tdatain_c (6) tdatain_c (5) tdatain_c (4) tdatain_c (3) tdatain_c (2) tdatain_c (1) tdatain_c (0) tclkc kgenb dn b tdatain_b (7) tdatain_b (6) tdatain_b (5) Input Input Output2 Input Input Input Input Input Input Input Input Input Input Input Input Input Input Input Input Input Input Input Input Input Input Input Input Input Input Input Routing In Out 0 1 2 3 4 5 6 7 8 9 10 11 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 12 -
QUAD GIGABIT ETHERNET DEVICE
Table 6. JTAG Pin Assignments (Continued)
S2204 Pin Name DINB4 DINB3 DINB2 DINB1 DINB0 TBCB DINA9 DINA8 DINA7 DINA6 DINA5 DINA4 DINA3 DINA2 DINA1 DINA0 TBCA RBC1D RBC0D DOUTD7 DOUTD6 DOUTD5 DOUTD4 DOUTD3 DOUTD2 DOUTD1 DOUTD0 COM_DETD DOUTD8 DOUTD9 RBC1C RBC0C DOUTC7 DOUTC6 DOUTC5 DOUTC4 DOUTC3 DOUTC2 DOUTC1 DOUTC0 Core_Scan Port Name tdatain_b (4) tdatain_b (3) tdatain_b (2) tdatain_b (1) tdatain_b (0) tclkb dna kgena tdatain_a (7) tdatain_a (6) tdatain_a (5) tdatain_a (4) tdatain_a (3) tdatain_a (2) tdatain_a (1) tdatain_a (0) tclka rcdp rcdn rdataout_d (7) rdataout_d (6) rdataout_d (5) rdataout_d (4) rdataout_d (3) rdataout_d (2) rdataout_d (1) rdataout_d (0) eofd_d kflagd_d errd_d rccp rccn rdataout_c (7) rdataout_c (6) rdataout_c (5) rdataout_c (4) rdataout_c (3) rdataout_c (2) rdataout_c (1) rdataout_c (0) JTAG Mode Input Input Input Input Input Input Input Input Input Input Input Input Input Input Input Input Input Output2 Output2 Output2 Output2 Output2 Output2 Output2 Output2 Output2 Output2 Output2 Output2 Output2 Output2 Output2 Output2 Output2 Output2 Output2 Output2 Output2 Output2 Output2 In Routing Out 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 -
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Table 6. JTAG Pin Assignments (Continued)
S2204 Pin Name DOUTC9 COM_DETC www..com DOUTC8 RBC1B RBC0B DOUTB8 DOUTB7 DOUTB6 DOUTB5 DOUTB4 DOUTB3 DOUTB2 DOUTB1 DOUTB0 COM_DETB DOUTB9 RBC1A RBC0A DOUTA9 DOUTA7 DOUTA6 DOUTA5 DOUTA4 DOUTA3 DOUTA2 DOUTA1 DOUTA0 COM_DETA DOUTA8 Core_Scan Port Name errd_c eofd_c kflag_c rcbp rcbn kflagd_b rdataout_b (7) rdataout_b (6) rdataout_b (5) rdataout_b (4) rdataout_b (3) rdataout_b (2) rdataout_b (1) rdataout_b (0) eofd_b errd_b rcap rcan errd_a rdataout_a (7) rdataout_a (6) rdataout_a (5) rdataout_a (4) rdataout_a (3) rdataout_a (2) rdataout_a (1) rdataout_a (0) eofd_a kflagd_a JTAG Mode Output2 Output2 Output2 Output2 Output2 Output2 Output2 Output2 Output2 Output2 Output2 Output2 Output2 Output2 Output2 Output2 Output2 Output2 Output2 Output2 Output2 Output2 Output2 Output2 Output2 Output2 Output2 Output2 Output2 Internal Routing In Out 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109
S2204
Table 6. JTAG Pin Assignments (Continued)
S2204 Core_Scan JTAG Routing Pin Name Port Name Mode In Out JTAG Control Pins (Ports that do not have a Boundary Scan Register) TCK TDI TDO TMS TRS jtag_tck jtag_tdi jtag_tdo jtag_tms jtag_trs -
Pins not JTAG Tested TXAP TXAN TXBP TXBN TXCP TXCN TXDP TXDN RATE RXAP RXAN RXBP RXBN RXCP RXCN RXDP RXDN -
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S2204
Table 7. Transmitter Input Pin Assignment and Descriptions
Pin Name
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Level TTL
I/O I
Pin # U15 U14 P12 R12 T13 T12 U13 P11 R11 T11 U12
Description Transmit Data for Channel A. Parallel data on this bus is clocked in on the rising edge of TBCA or REFCLK. (See Table 1.)
DINA8 DINA7 DINA6 DINA5 DINA4 DINA3 DINA2 DINA1 DINA0 TBCA TTL I
Transmit Byte Clock A. When TMODE is High, this signal is used to clock Data on DINA[0:9] into the S2204. When TMODE is Low, TBCA is ignored. Transmit Byte for Channel B. Parallel data on this bus is clocked in on the rising edge of TBCB or REFCLK. (See Table 1.)
DINB9 DINB8 DINB7 DINB6 DINB5 DINB4 DINB3 DINB2 DINB1 DINB0 TBCB
TTL
I
R16 T16 R15 P14 T15 R14 U17 U16 P13 T14 R13
TTL
I
Transmit Byte Clock B. When TMODE is High, this signal is used to clock Data on DINB[0:9] into the S2204. When TMODE is Low, TBCB is ignored. Transmit Data for Channel C. Parallel data on this bus is clocked in on the rising edge of TBCC or REFCLK. (See Table 1.)
DINC9 DINC8 DINC7 DINC6 DINC5 DINC4 DINC3 DINC2 DINC1 DINC0 TBCC
TTL
I
N17 P17 M15 N16 M14 R17 P16 N15 T17 N14 P15
TTL
I
Transmit Byte Clock C. When TMODE is High, this signal is used to clock Data on DINC[0:9] into the S2204. When TMODE is Low, TBCC is ignored.
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Table 7. Transmitter Signal Descriptions (Continued)
Pin Name
www..com DIND9
S2204
Level TTL
I/O I
Pin # J16 K17 L17 K16 K15 K14 M17 L16 M16 L15 L14
Description Transmit Data for Channel D. Parallel data on this bus is clocked in on the rising edge of TBCD or REFCLK. (See Table 1.)
DIND8 DIND7 DIND6 DIND5 DIND4 DIND3 DIND2 DIND1 DIND0 TBCD TTL I
Transmit Byte Clock D. When TMODE is High, this signal is used to clock Data on DIND[0:9] into the S2204. When TMODE is Low, TBCD is ignored.
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S2204
Table 8. Transmitter Output Signals
Pin Name
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Level Diff. LVPECL Diff. LVPECL Diff. LVPECL Diff. LVPECL TTL
I/O O
Pin # A17 B17 C17 D17 E17 F16 F17 G17 J14
Description High speed serial outputs for Channel A.
TXAN TXBP TXBN TXCP TXCN TXDP TXDN TCLKO
O
High speed serial outputs for Channel B.
O
High speed serial outputs for Channel C.
O
High speed serial outputs for Channel D.
O
TTL Output Clock at the Parallel data rate. This clock is provided for use by up-stream circuitry.
Table 9. Mode Control Signals
Pin Name TESTMODE Level TTL I/O I Pin # E4 Description Test Mode Control. Keep Low for normal operation.
TESTMODE1
TTL
I
D4
Test Mode Control. Keep Low for normal operation.
TMODE
TTL
I
B13
Transmit Mode Control. Controls the source of the clock used to input and output data to and from the S2204. When TMODE is Low, REFCLK is used to clock data on DINx[0:9] into the S2204. TBCA is used to clock parallel data DOUTx[0:9] out of the device. When TMODE is High, the TBCx inputs are used to clock data into their respective channels. The output clocks are derived from the receiver's CRUs. REFCLK Select Input. This signal configures the PLL for the appropriate REFCLK frequency. When CLKSEL = 0, the REFCLK frequency equals the parallel word rate. When CLKSEL = 1, the REFCLK frequency is 1/2 the parallel data rate. Reference Clock is used for the transmit VCO and frequency check for the clock recovered from the receiver serial data. Also used to clock parallel data into the device when in REFCLK mode. When Low, the S2204 is held in reset. The receiver PLL is forced to lock to the REFCLK. The FIFOs are initialized on the rising edge of RESET. When High, the S2204 operates normally. When Low, the S2204 operates with the serial output rate equal to the VCO frequency. When High, the S2204 operates with the VCO internally divided by 2 for all functions.
CLKSEL
TTL
I
C12
REFCLK
TTL
I
H17
RESET
TTL
I
C15
RATE
TTL
I
D12
Note: All TTL inputs except REFCLK have internal pull-up networks.
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July 16, 1999 / Revision C
QUAD GIGABIT ETHERNET DEVICE
Table 10. Receiver Output Pin Assignment and Descriptions
Pin Name
www..com DOUTA9
S2204
Level TTL
I/O O
Pin # G1 G3 J1 J3 J2 H1 H2 H3 F1 G2 F2
Description Channel A Receiver Data Outputs. Parallel data on this bus is valid on the rising edge of RBC1A in full clock mode and valid on the rising edge of both RBC1A and RBC0A in half clock mode.
DOUTA8 DOUTA7 DOUTA6 DOUTA5 DOUTA4 DOUTA3 DOUTA2 DOUTA1 DOUTA0 COM_DETA TTL O
Channel A Comma Detect. A High on this output indicates that a valid K28.5 has been detected and is present on the parallel data outputs DOUTA[0:9]. Receive Byte Clocks. Parallel receive data, DOUTA[0:9] and COM_DETA are valid on the rising edge of RBC1A when in full clock mode and valid on the rising edge of both RBC1A and RBC0A in half clock mode. Channel B Receiver Data Outputs. Parallel data on this bus is valid on the rising edge of RBC1B in full clock mode and valid on the rising edge of both RBC1B and RBC0B in half clock mode.
RBC1A RBC0A
TTL
O
K2 K1
DOUTB9 DOUTB8 DOUTB7 DOUTB6 DOUTB5 DOUTB4 DOUTB3 DOUTB2 DOUTB1 DOUTB0 COM_DETB
TTL
O
K3 P2 R1 P1 M3 N2 M2 N1 L2 M1 L1
TTL
O
Channel B Comma Detect. A High on this output indicates that a valid K28.5 has been detected and is present on the parallel data outputs DOUTB[0:9]. Receive Byte Clocks. Parallel receive data, DOUTB[0:9] and COM_DETB are valid on the rising edge of RBC1B when in full clock mode and valid on the rising edge of both RBC1B and RBC0B in half clock mode. Channel C Receiver Data Outputs. Parallel data on this bus is valid on the rising edge of RBC1C in full clock mode and valid on the rising edge of both RBC1C and RBC0C in half clock mode.
RBC1B RBC0B
TTL
O
U1 T1
DOUTC9 DOUTC8 DOUTC7 DOUTC6 DOUTC5 DOUTC4 DOUTC3 DOUTC2 DOUTC1 DOUTC0 COM_DETC
TTL
O
T2 P3 R7 R6 T5 U3 T4 R5 U2 T3 R2
TTL
O
Channel C Comma Detect. A High on this output indicates that a valid K28.5 has been detected and is present on the parallel data outputs DOUTC[0:9].
July 16, 1999 / Revision C
17
S2204
QUAD GIGABIT ETHERNET DEVICE
Table 10. Receiver Output Pin Assignment and Descriptions (Continued)
Pin Name
www..com RBC1C
Level TTL
I/O O
Pin # U5 U4
Description Receive Byte Clocks. Parallel receive data, DOUTC[0:9] and COM_DETC are valid on the rising edge of RBC1C when in full clock mode and valid on the rising edge of both RBC1C and RBC0C in half clock mode. Channel D Receiver Data Outputs. Parallel data on this bus is valid on the rising edge of RBC1D in full clock mode and valid on the rising edge of both RBC1D and RBC0D in half clock mode.
RBC0C
DOUTD9 DOUTD8 DOUTD7 DOUTD6 DOUTD5 DOUTD4 DOUTD3 DOUTD2 DOUTD1 DOUTD0 COM_DETD
TTL
O
T6 T7 U11 R10 U9 R9 T9 U8 U7 T8 U6
TTL
O
Channel D Comma Detect. A High on this output indicates that a valid K28.5 has been detected and is present on the parallel data outputs DOUTD[0:9]. Receive Byte Clocks. Parallel receive data, DOUTD[0:9] and COM_DETD are valid on the rising edge of RBC1D when in full clock mode and valid on the rising edge of both RBC1D and RBC0D in half clock mode.
RBC1D RBC0D
TTL
O
T10 U10
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July 16, 1999 / Revision C
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Table 11. Receiver Input Pin Assignment and Descriptions
Pin Name
www..com RXAP
S2204
Level Diff. LVPECL Diff. LVPECL Diff. LVPECL Diff. LVPECL
I/O I
Pin # A2 A3 A5 B5 A8 A9 B11 B12
Description Differential LVPECL compatible inputs for channel A. RXAP is the positive input, RXAN is the negative. Internally biased to VDD -1.3V for AC coupled applications. Differential LVPECL compatible inputs for channel B. RXBP is the positive input, RXBN is the negative. Internally biased to VDD -1.3V for AC coupled applications. Differential LVPECL compatible inputs for channel C. RXCP is the positive input, RXCN is the negative. Internally biased to VDD -1.3V for AC coupled applications. Differential LVPECL compatible inputs for channel D. RXDP is the positive input, RXDN is the negative. Internally biased to VDD -1.3V for AC coupled applications.
RXAN RXBP RXBN RXCP RXCN RXDP RXDN
I
I
I
Table 12. Receiver Control Signals
Pin Name LPENA LPENB LPENC LPEND CMODE Level TTL I/O I Pin # D14 G14 G15 H14 C2 Description Loopback Enable. When Low, input source is the high speed serial input for each channel. When High, the serial output for each channel is looped back to its input. Clock Mode Control. When Low, the parallel output clocks (RBC1/0x) rate is equal to 1/2 the data rate. When High, the parallel output clocks (RBC1/0x) rate is equal to the data rate.
TTL
I
Note: All TTL inputs except REFCLKhave internal pull-up networks.
Table 13. Power and Ground Signals
Pin Name VDDA Qty. 5 Pin # A1, A6, Analog Power (VDD) low noise. A13, A16, C8 B7, B8, B15, C4, D11 Analog Ground (VSS). Description
VSSA
5
VDD
6
A12, A15, Power for High Speed Circuitry (VDD). B4, B6, C6, D9 A4, A7, Ground for High Speed Circuitry (VSS). A11, A14, B10, B14, C13, D5, D6, D8
VSS VSSSUB
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July 16, 1999 / Revision C
19
S2204
Table 13. Power and Ground Signals (Continued)
Pin Name
www..com PECLPWR
QUAD GIGABIT ETHERNET DEVICE
Qty. 4
Pin # D15, E15, PECL Power (VDD) E16, G16 C16 H16 B1, B2, E3, J17, L4, P9 C1, C3, D2, F4, J15, N4, P10, R3 E1, G4, H4, K4, N3, P5, P7, P8 D1, E2, F3, J4, L3, M4 P4, P6, R4, R8 B16 D3 D13 C14 PECL Ground (VSS)
Description
PECLGND
2
DIGPWR
6
Core Circuitry Power (VDD)
DIGGND
8
Core Circuitry Ground (VSS)
TTLPWR
8
Power for TTL I/O (VDD)
TTLGND
10
Ground for TTL I/O (VSS)
PWR
2
Power
CAP1 CAP2 NC
2
Pins for external loop filter capacitor
10
B9, C5, Not Connected. Used as Test Pins. Do Not Connect. C7, C9, C11, D7, D16, E14, F14, F15
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July 16, 1999 / Revision C
QUAD GIGABIT ETHERNET DEVICE
Table 14. JTAG Test Signals
Pin Name
www..com
S2204
Level
I/O
Pin #
Description
TMS
TTL
I
A10
Test Mode Select. Enables JTAG testing of device.
TCK
TTL
I
C10
Test Clock. JTAG test clock.
TDI
TTL
I O TRISTATE I
D10
Test Data In. JTAG data input. Test Data Out. JTAG data output. Can be high impedance under JTAG controller command. Test Reset. Resets JTAG test state machine.
TDO
TTL
H15
TRS
TTL
B3
July 16, 1999 / Revision C
21
S2204
Figure 9. S2204 Pinout (Bottom View)
A B C D E F G H J K
QUAD GIGABIT ETHERNET DEVICE
L
M
N
P
R
T
U
1 VDDA www..com
DIGPWR
DIGGND
TTLGND
TTLPWR
DOUTA1
DOUTA9
DOUTA4
DOUTA7
RBC0A
COM_ DETB
DOUTB0
DOUTB2
DOUTB6
DOUTB7
RBC0B
RBC1B
2
RXAP
DIGPWR
CMODE
DIGGND
TTLGND
COM_ DE TA
DOUTA0
DOUTA3
DOUTA5
RBC1A
DOUTB1
DOUTB3
DOUTB4
DOUTB8
COM_ DETC
DOUTC9
DOUTC1
3
RXAN
TRS
DIGGND
PWR
DIGPWR
TTLGND
DOUTA8
DOUTA2
DOUTA6
DOUTB9
TTLGND
DOUTB5
TTLPWR
DOUTC8
DIGGND
DOUTC0
DOUTC4
4
VSS
VDD
VSSA
TE S T MODE1
TEST MODE
DIGGND
TTLPWR
TTLPWR
TTLGND
TTLPWR
DIGPWR
TTLGND
DIGGND
TTL G ND
TTLGND
DOUTC3
RBC0C
5
RXBP
RXBN
NC
VSSSUB
TTLPWR
DOUTC2
DOUTC5
RBC1C
6
VDDA
VDD
VDD
VS S
TTLGND
DOUTC6
DOUTD9
COM_ DETD
7
VSSSUB
VSS A
NC
NC
TTLPWR
DOUTC7
DOUTD8
DOUTD1
8
RXCP
VSSA
VDDA
VSSSUB
TTLPWR
TTLGND
DOUTD0
DOUTD2
9
RXCN
NC
NC
VDD
DIGPWR
DOUTD4
DOUTD3
DOUTD5
10
TMS
VS S
TCK
TDI
DIGGND
DOUTD6
RBC1D
RBC0D
11
VSS
RXDP
NC
VSS A
DINA2
DINA1
DINA0
DOUTD7
12
VDD
RXDN
CLKSEL
RATE
DINA7
DINA6
DINA4
TBCA
13
VDDA
TMODE
VSSSUB
CA P 1
DINB1
T B CB
DINA5
DINA3
14
VSSSUB
VSS
CAP2
LPEN A
NC
NC
LPENB
LPEN D
TCLKO
DIND4
TBCD
DINC5
DINC0
DINB6
DINB4
DINB0
DINA8
15
VDD
VSSA
RESET
PECL PWR
PECL PWR PECL PWR
NC
L P E NC
TDO
DIGGND
DIND5
DIND0
DINC7
DINC2
T B CC
DINB7
DINB5
DINA9
16
VDDA
PWR
PECLGND
NC
TXCN
P E CL PWR
PECLGND
DIND9
DIND6
DIND2
DIND1
DINC6
DINC3
DINB9
DINB8
DINB2
17
TXAP
TXAN
TXBP
TXBN
TXCP
TXDP
TXDN
REFCLK
DIGPWR
DIND8
DIND7
DIND3
DINC9
DINC8
DINC4
DINC1
DINB3
Note: NC used as test pins. Do Not Connect.
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July 16, 1999 / Revision C
QUAD GIGABIT ETHERNET DEVICE
Figure 10. S2204 Pinout (Top View)
U T R P N M L K J H G F E D C B A
S2204
RBC1B RBC0B www..com
DOUTB7
DOUTB6
DOUTB2
DOUTB0
COM_ DETB
RBC0A
DOUTA7
DOUTA4
DOUTA9
DOUTA1
TTLPWR
TTLGND
DIGGND
DIGPWR
VDDA
1
DOUTC1
DOUTC9
COM_ DETC
DOUTB8
DOUTB4
DOUTB3
DOUTB1
RBC1A
DOUTA5
DOUTA3
DOUTA0
COM_ DETA
TTLGND
DIGGND
CMODE
DIGPWR
RXAP
2
DOUTC4
DOUTC0
DIGGND
DOUTC8
TTLPWR
DOUTB5
TTLGND
DOUTB9
DOUTA6
DOUTA2
DOUTA8
TTLGND
DIGPWR
PWR
DIGGND
TRS
RXAN
3
RBC0C
DOUTC3
TTLGND
TTLGND
DIGGND
TTLGND
DIGPWR
TTLPWR
TTLGND
TTLPWR
TTLPWR
DIGGND
TEST MODE
TEST MODE1
VSSA
VDD
VSS
4
RBC1C
DOUTC5
DOUTC2
TTLPWR
V S S S UB
NC
RXBN
RXBP
5
COM_ DETD
DOUTD9
DOUTC6
TTLGND
VSS
VD D
VDD
VDDA
6
DOUTD1
DOUTD8
DOUTC7
TTLPWR
NC
NC
VSSA
VSSSUB
7
DOUTD2
DOUTD0
TTLGND
TTL P WR
V S S S UB
VDDA
VSSA
RXCP
8
DOUTD5
DOUTD3
DOUTD4
DIGPWR
VDD
NC
NC
RXCN
9
RBC0D
RBC1D
DOUTD6
DIGGND
TDI
TCK
VS S
TMS
10
DOUTD7
DINA0
DINA1
DINA2
VSSA
NC
RXDP
VS S
11
TBCA
DINA4
DINA6
DINA7
RATE
CLKSEL
RXDN
VDD
12
DINA3
DINA5
TBCB
DINB1
CAP1
VSSSUB
TMODE
VDDA
13
DINA8
DINB0
DINB4
DINB6
DINC0
DINC5
TBCD
DIND4
TCLKO
LPEN D
LPENB
NC
NC
LPENA
CA P 2
VSS
VSSSU B
14
DINA9
DINB5
DINB7
TBCC
DINC2
DINC7
DIND0
DIND5
DIGGND
TDO
LPENC
NC
PECL PWR PECL PWR
P E CL PWR
RESET
VSS A
VDD
15
DINB2
DINB8
DINB9
DINC3
DINC6
DIND1
DIND2
DIND6
DIND9
PECLGND
P E CL PWR
TXCN
NC
PECLGND
PWR
VDDA
16
DINB3
DINC1
DINC4
DINC8
DINC9
DIND3
DIND7
DIND8
DIGPWR
REFCLK
TXDN
TXDP
TXCP
TXBN
TX B P
TXAN
TXAP
17
Note: NC used as test pins. Do Not Connect.
July 16, 1999 / Revision C
23
S2204
Figure 11. Compact 23mm x 23mm 208 TBGA Package
QUAD GIGABIT ETHERNET DEVICE
www..com
Thermal Management
Device
S2204
ja (Still Air)
14 C/W
jc
0.8 C/W
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July 16, 1999 / Revision C
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Figure 12. Transmitter Timing (REFCLK Mode, TMODE = 0)
S2204
REFCLK
www..com
DINx[0:9] T1 T2
SERIAL DATA OUT
Table 15. S2204 Transmitter Timing (REFCLK Mode, TMODE = 0)
Parameters T1 T2 Description Data Setup w.r.t. REFCLK Data Hold w.r.t. REFCLK Min 0.5 1.5 Max Units ns ns Conditions See Note 1.
1. All AC measurements are made from the reference voltage levels of the clock (1.4V) to the valid input or output data levels (.8V or 2.0V).
Figure 13. Transmitter Timing (TBC Mode, TMODE = 1)
TBCx
DINx[0:9] T1 T2
SERIAL DATA OUT
Table 16. S2204 Transmitter Timing (TBC Mode, TMODE = 1)
Parameters T1 T2 Description Data Setup w.r.t. TBC Data Hold w.r.t. TBC Phase drift between TBCx and REFCLK Min 1.0 0.5 -3 Max +3 Units ns ns ns Conditions See Note 1.
1. All AC measurements are made from the reference voltage levels of the clock (1.4V) to the valid input or output data levels (.8V or 2.0V).
July 16, 1999 / Revision C
25
S2204
Table 17. S2204 Receiver Timing (Full and Half Clock Mode)
Parameters T3 www..com T4 T5 T6 T7 TR1, TF1 TR0, TF0 TDR, TDF Duty Cycle Description Data Setup w.r.t. RBC1/0x Data Hold w.r.t. RBC1/0x Data Setup w.r.t. RBC1/0x Data Hold w.r.t. RBC1/0x Time from RBC1x rise to RBC0x rise RBC1x Rise and Fall Times RBC0x Rise and Fall Times DOUTx Rise and Fall Times RBC1/0x Duty Cycle 40 Min 2.5 2.5 2.5 2.5 7.5
QUAD GIGABIT ETHERNET DEVICE
Max
Units ns ns ns ns
Conditions at 1.25 Gbps 1,2 TMODE = 1 TMODE = 1 at 1.25 Gbps 1,2 TMODE = 1 TMODE = 1 at 1.25 Gbps 1,2 See note 2. See Figure 19. See note 2. See Figure 19. See note 2. See Figure 18. See note 1.
8.5 2.4 2.4 2.4 60
ns ns ns ns %
1. Measurements made from the reference voltage levels of the clock (1.4V) to the valid input or output data levels (.8V or 2.0V). 2. TTL/CMOS AC timing measurements are assumed to have an output load of 10pf.
Table 18. S2204 Receiver Timing (External Clock Mode)
Parameters T8 Description TBCA to DOUTx Propagation Delay Min 3.0 Max 8.0 Units ns Conditions 10 pf load capacitance at the end of a 3 inch 50 transmission line.
1. Measurements made from the reference voltage levels of the clock (1.4V) to the valid input or output data levels (.8V or 2.0V).
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July 16, 1999 / Revision C
QUAD GIGABIT ETHERNET DEVICE
Figure 14. Receiver Timing (Full Clock Mode, CMODE = 1)
SERIAL DATA IN
S2204
www..com
RBC0x
RBC1x
DOUTx[0:9], COM_DETx T3 T4
Figure 15. Receiver Timing (Half Clock Mode, CMODE = 0, TMODE = 1)
SERIAL DATA IN
RBC0x
RBC1x
DOUTx[0:9], COM_DETx T5 T6 T7 T5 T6
Figure 16. Receiver Timing (External Clock Mode) (TBCA to DATA Propagation Delay, TMODE = 0)
SERIAL DATA IN
TBCA (Input)
DOUTx[0:9], COM_DETx T8
July 16, 1999 / Revision C
27
S2204
Figure 17. TCLKO Timing
QUAD GIGABIT ETHERNET DEVICE
w w w . d aREFCLKe e t 4 u . c o m tash
T9 TCLKO
Table 19. S2204 Transmitter (TCLKO Timing)
Parameters T9 Description TCLKO w.r.t. REFCLK TCLKO Duty Cycle
Note: Measurements are made at 1.4V level of clocks.
Min 1.0 45%
Max 6.5 55%
Units ns %
Conditions
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July 16, 1999 / Revision C
QUAD GIGABIT ETHERNET DEVICE
Table 20. Absolute Maximum Ratings
Parameter Storage Temperature
www..com
S2204
Min -65 -0.5 -0.5 0
Typ
Max 150 +5.0 3.47 VDD 8 8 25
Units C V V V mA mA mA
Voltage on VDD with Respect to GND Voltage on any TTL Input Pin Voltage on any PECL Input Pin TTL Output Sink Current TTL Output Source Current High Speed PECL Output Source Current ESD Sensitivity
1
Over 500 V
1. Human body model.
Table 21. Recommended Operating Conditions
Parameter Ambient Temperature Under Bias Junction Temperature Under Bias Voltage on any Power Pin with respect to GND/VSS Voltage on TTL Input Pin Voltage on any PECL Input Pin 3.13 0 VDD -2V 3.3 Min 0 Typ Max 70 130 3.47 3.47 VDD Units C C V V V
Table 22. Reference Clock Requirements
Parameters FT TD1-2 TRCR, TRCF -- Description Frequency Tolerance Symmetry REFCLK Rise and Fall Time Jitter Min -100 40 Max +100 60 2 80 Units ppm % ns ps Duty Cycle at 50% pt. 20% - 80%. Peak-to-Peak, to maintain 77% eye opening. Conditions
July 16, 1999 / Revision C
29
S2204
Table 23. Serial Data Timing, Transmit Outputs
Parameters Total Jitter
www..com
QUAD GIGABIT ETHERNET DEVICE
Description Serial Data Output total jitter Serial Data Output deterministic jitter Serial Data Output rise and fall time
Min
Typ
Max 192 80 300
Units ps ps ps
Comments Peak-to-Peak. Peak-to-Peak. 20% - 80%.
TDJ
TSR, TSF
Table 24. Serial Data Timing, Receive Inputs
Parameters TLOCK (Startup) TLOCK (Reacquire) TDJ Input Jitter Tolerance RSR, RSF Description Startup Acquisition Lock Time at 1.25 Gbps Min Typ Max 2.5 150 Data Acquisition Lock Time at (1.25G) 180 Deterministic Input Jitter Tolerance Serial Data Input total jitter tolerance Serial Data Input rise and fall time 370 59 9 330 ns ps ps ps Units s ns Comments 8B/10B idle pattern sample basis, from device start up. 90% Input data eye. (See Figure 23.) 70% Input data eye. As specified by IEEE 802.3z. Peak-to-Peak, as specified by IEEE 802.3z. 20% - 80%.
Table 25. DC Characteristics
Parameters VOH VOL VIH VIL IIH IIL IDD PD VDIFF VOUT CIN Description Output High Voltage (TTL) Output Low Voltage (TTL) Input High Voltage (TTL) Input Low Voltage (TTL) Input High Current (TTL) Input Low Current (TTL) Supply Current Power Dissipation Min. differential input voltage swing for differential PECL inputs Differential Serial Output Voltage Swing Input Capacitance 100 1400 760 2.5 Min 2.4 GND 2.0 GN D 0.8 40 600 980 3.4 2600 2600 3 Typ 2.8 .025 Max VDD 0.5 Units V V V V A A mA W mV mV pf VIN = 2.4 V, VDD = Max VIN = .8 V, VDD = Max 1010 Pattern. 1010 Pattern. See Figure 21. See Figure 20. Conditions VDD = min IOH = -4mA VDD = min IOL = 4mA
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July 16, 1999 / Revision C
QUAD GIGABIT ETHERNET DEVICE
OUTPUT LOAD
The S2204 serial outputs do not require output pulldown resistors.
www..com ACQUISITION
S2204
Figure 21. High Speed Differential Inputs
VDD - 1.3 V 0.01 f
TIME
With the input eye diagram shown in Figure 23, the S2204 will recover data with a 1E-9 BER within the time specified by TLOCK in Table 24 after an instantaneous phase shift of the incoming data.
0.01 f
100
Figure 18. Serial Input/Output Rise and Fall Time
80% 50% 20% Tr Tf 80% 50% 20%
Figure 22. Receiver Input Eye Diagram Jitter Mask
Bit Time
Amplitude
Figure 19. TTL Input/Output Rise and Fall Time
+2.0V +0.8V Tr Tf +2.0V +0.8V
24%
Figure 20. Serial Output Load
Figure 23. Acquisition Time Eye Diagram
1.3
Normalized Amplitude
VDD -2.3V 0.01 f
1.0 0.8 0.7 0.5 0.3 0.2
0.0 0.05 0.1 0.9 0.95 1.0
0.01 f
0.0
0.3
0.4
Normalized Time
0.6
0.7
July 16, 1999 / Revision C
31
S2204
Figure 24. Loop Filter Capacitor Connections
QUAD GIGABIT ETHERNET DEVICE
www..com
270 CAP1 22 nf CAP2 270
S2204
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July 16, 1999 / Revision C
QUAD GIGABIT ETHERNET DEVICE
Ordering Information
PREFIX
www..com
S2204
DEVICE
PACKAGE
S- Integrated Circuit
2204
TB - 208 TBGA
X Prefix
XXXX Device
XX Package
IS
O 90 0
D
1
IFI
Applied Micro Circuits Corporation * 6290 Sequence Dr., San Diego, CA 92121 Phone: (858) 450-9333 * (800) 755-2622 * Fax: (858) 450-9885 http://www.amcc.com
AMCC reserves the right to make changes to its products or to discontinue any semiconductor product or service without notice, and advises its customers to obtain the latest version of relevant information to verify, before placing orders, that the information being relied on is current. AMCC does not assume any liability arising out of the application or use of any product or circuit described herein, neither does it convey any license under its patent rights nor the rights of others. AMCC reserves the right to ship devices of higher grade in place of those of lower grade. AMCC SEMICONDUCTOR PRODUCTS ARE NOT DESIGNED, INTENDED, AUTHORIZED, OR WARRANTED TO BE SUITABLE FOR USE IN LIFE-SUPPORT APPLICATIONS, DEVICES OR SYSTEMS OR OTHER CRITICAL APPLICATIONS. AMCC is a registered trademark of Applied Micro Circuits Corporation. Copyright (R) 1998 Applied Micro Circuits Corporation
E
CE
RT
July 16, 1999 / Revision C
33

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